RX-4045SAAA0 PURE SN

MAX77278 I 2C-Compatible Serial Interface Implementation Guide UG6474; Rev 0; 9/17 Abstract This document serves as a guide to engineers designing with the MAX77278 serial interface. It details the various communication protocols implemented in the 2-wire serial interface block of the MAX77278, as well as some general information on the I2C specification. Maxim Integrated Page 1 of 15 Table of Contents Overview .............................................................................................................................................................................4 Features ...............................................................................................................................................................................4 Simplified Block Diagram ................................................................................................................................................ 5 System Configuration ...................................................................................................................................................... 5 Hardware Implementation and Interface Power ...................................................................................................... 6 Data Transfer ..................................................................................................................................................................... 6 START and STOP Conditions ........................................................................................................................................ 6 Acknowledge Bit................................................................................................................................................................ 7 Slave Address..................................................................................................................................................................... 7 Clock Stretching ................................................................................................................................................................ 7 General Call Address ....................................................................................................................................................... 7 Device ID ............................................................................................................................................................................. 7 Communication Speed .................................................................................................................................................... 8 Communication Protocols .............................................................................................................................................. 9 Writing to a Single Register ....................................................................................................................................... 9 Writing Multiple Bytes to Sequential Registers ................................................................................................. 10 Reading from a Single Register ............................................................................................................................... 12 Reading from Sequential Registers ........................................................................................................................ 13 Engaging High-Speed Mode (HS-Mode) for Operation Up to 3.4MHz ...................................................... 14 Revision History............................................................................................................................................................... 15 Maxim Integrated Page 2 of 15 List of Figures Figure 1. Simplified block diagram. ............................................................................................................................... 5 Figure 2. I2C system configuration. .............................................................................................................................. 5 Figure 3. I2C START and STOP conditions. ................................................................................................................ 6 Figure 4. Writing to a single register. .......................................................................................................................... 9 Figure 5. Writing multiple bytes................................................................................................................................... 11 Figure 6. Reading from a single register.................................................................................................................... 12 Figure 7. Reading from multiple registers................................................................................................................. 13 Figure 8. Engaging high-speed mode......................................................................................................................... 14 List of Tables Table 1. MAX77278 Slave Addresses ......................................................................................................................... 7 Maxim Integrated Page 3 of 15 Overview The MAX77278 features a revision 3.0 I2C-compatible, 2-wire serial interface consisting of a bidirectional serial data line (SDA) and a serial clock line (SCL). As shown in the Simplified Block Diagram, the I2C SDA and SCL signals are internally decoded by the devices used to communicate with the top-level control logic as well as the charger, LDO, and current sinks. The MAX77278 is a slave-only device that relies on an external bus master to generate SCL. SCL clock rates from 0Hz to 3.4MHz are supported. I2C is an open-drain bus and, therefore, SDA and SCL require pullups. The MAX77278 I2C communication controller implements 7-bit slave addressing. An I2C bus master initiates communication with the slave by issuing a START condition followed by the slave address. The OTP address is factory programmable for one of two options. All slave addresses not mentioned in the slave address table (Table 1) are not acknowledged. The devices use 8-bit registers with 8-bit register addressing. They support standard communication protocols: (1) writing to a single register, (2) writing to multiple sequential registers with an automatically incrementing data pointer, (3) reading from a single register, and (4) reading from multiple sequential registers with an automatically incrementing data pointer. For additional information on the I2C protocols, refer to the I2C bus specification available from NXP (Philips) Semiconductors. Features • I2C Revision 3-Compatible Serial Communications Channel • 0Hz to 100kHz (Standard Mode) • 0Hz to 400kHz (Fast Mode) • 0Hz to 1MHz (Fast Mode Plus) • 0Hz to 3.4MHz (High-Speed Mode) • Does not utilize I2C clock stretching Maxim Integrated Page 4 of 15 Simplified Block Diagram Figure 1. Simplified block diagram. System Configuration The I2C bus is a multimaster bus. The maximum number of devices that can attach to the bus is only limited by bus capacitance. A device on the I2C bus that sends data to the bus is called a transmitter. A device that receives data from the bus is called a receiver. The device that initiates a data transfer and generates the SCL clock signals to control the data transfer is a master. Any device that is being addressed by the master is considered a slave. The MAX77278 I2C-compatible interface operates as a slave on the I2C bus with transmit and receive capabilities. Figure 2. I2C system configuration. Maxim Integrated Page 5 of 15 Hardware Implementation and Interface Power The MAX77278 I2C interface derives its power from VIO. Typically, a power input such as VIO would require a local 0.1μF ceramic bypass capacitor to ground. However, in highly integrated power distribution systems, a dedicated capacitor might not be necessary. If the impedance between VIO and the next closest capacitor (≥ 0.1μF) is less than 100mΩ in series with 10nH, then a local capacitor is not needed. Otherwise, bypass VIO to GND with a 0.1µF ceramic capacitor. VIO accepts voltages from 1.7V to 3.6V. Cycling VIO does not reset the I2C registers. VSYS must drop below SYSPOR for the registers to reset. When VIO is less than VIOUVLO and VSYS is less than VSYSUVLO, SDA and SCL are high impedance. Note that I2C is an open-drain bus and requires pullup resistors. Typical applications place these pullups near the host controller. Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals. See the I2C START and STOP Conditions section. Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is nine bits long: eight bits of data followed by the acknowledge bit. Data is transferred with the MSB first. START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high. A START condition from the master signals the beginning of a transmission to the MAX77278. The master terminates transmission by issuing a not-acknowledge followed by a STOP condition (see the Acknowledge Bit section for information on not-acknowledge). The STOP condition frees the bus. To issue a series of commands to the slave, the master can issue repeated START (Sr) commands instead of a STOP command to maintain control of the bus. In general, a repeated START command is functionally equivalent to a regular START command. When a STOP condition or incorrect address is detected, the MAX77278 internally disconnects SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough. Figure 3. I2C START and STOP conditions. Maxim Integrated Page 6 of 15 Acknowledge Bit Both the I2C bus master and the MAX77278 (slave) generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each 9-bit data packet. To generate an acknowledge (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge (NA), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The MAX77278 issues an ACK for all register addresses in the possible address space even if the particular register does not exist. Slave Address Refer to the I2C Serial Interface and the Ordering Information section of the MAX77278 IC data sheet for more information. Table 1. MAX77278 Slave Addresses ADDRESS 7-BIT SLAVE ADDRESS 8-BIT WRITE ADDRESS 8-BIT READ ADDRESS Main Address (ADDR = 1) 0x48, 0b 100 1000 0x90 0b 1001 0000 0x91, 0b 1001 0001 Main Address (ADDR= 0) 0x40, 0b 100 0000 0x80, 0b 1000 0000 0x81, 0b 1000 0001 Other Acknowledges 0x25, 0b 010 0101 0x50, 0b 101 0000 0x4A, 0b 0100 1010 0xA0, 0b 1010 0000 0x4B, 0b 0100 1011 0xA1, 0b 1010 0001 Test Mode 0x49, 0b 100 1001 0x5A, 0b 101 1001 0x68, 0b 110 1000 0x92, 0b 1001 0010 0xB2, 0b 1011 0010 0xD0, 0b 1101 0000 0x93, 0b 1001 0011 0xB3, 0b 1011 0011 0xD1, 0b 1101 0001 Clock Stretching In general, the clock signal generation for the I2C bus is the responsibility of the master device. The I2C specification allows slow slave devices to alter the clock signal by holding down the clock line. The process in which a slave device holds down the clock line is typically called clock stretching. The MAX77278 does not use any form of clock stretching to hold down the clock line. General Call Address The MAX77278 does not implement the I2C specification’s general call address. If the MAX77278 sees the general call address (0b0000_0000), it does not issue an acknowledge. Device ID The MAX77278 does not support the I2C Device ID feature. Maxim Integrated Page 7 of 15 Communication Speed The MAX77278 is compatible with all four communication speed ranges as defined by the Revision 3 I2C specification: • • • • 0Hz to 100kHz (Standard Mode) 0Hz to 400kHz (Fast Mode) 0Hz to 1MHz (Fast Mode Plus) 0Hz to 3.4MHz (High-Speed Mode) Operating in standard mode, fast mode, and fast mode plus does not require any special protocols. The main consideration when changing the bus speed through this range is the combination of the bus capacitance and pullup resistors. Higher time constants created by the bus capacitance and pullup resistance (C x R) slow the bus operation. Therefore, when increasing bus speeds, the pullup resistance must be decreased to maintain a reasonable time constant. Refer to the Pullup Resistor Sizing section of the I2C bus specification and user manual (available for free online) for detailed guidance on the pullup resistor selection. In general, for bus capacitances of 200pF, a 100kHz bus needs 5.6kΩ pullup resistors, a 400kHz bus needs approximately 1.5kΩ pullup resistors, and a 1MHz bus needs 680Ω pullup resistors. Note that when the open-drain bus is low, the pullup resistor is dissipating power, and lower value pullup resistors dissipate more power (V2/R). Operating in high-speed mode requires some special considerations. For a full list of considerations, refer to the I2C bus specification and user manual. The major considerations with respect to the MAX77278 include the following: • • • The I2C bus master should use current source pullups to shorten the signal rise time. The I2C slave must use a different set of input filters on its SDA and SCL lines to accommodate for the higher bus speed. The communication protocols need to utilize the high-speed master code. At power-up and after each STOP condition, the MAX77278 input filters are set for standard mode, fast mode, and fast mode plus (i.e., 0Hz to 1MHz). To switch the input filters for high-speed mode, use the high-speed master code protocols that are described in the Communication Protocols section. Maxim Integrated Page 8 of 15 Communication Protocols The MAX77278 supports both writing and reading from its registers. Writing to a Single Register Figure 4 shows the protocol for the I2C master device to write one byte of data to the MAX77278. This protocol is the same as the SMBus specification’s write-byte protocol. The write-byte protocol is as follows: 1. The master sends a START command (S). 2. The master sends the 7-bit slave address followed by a write bit (R/W = 0). 3. The addressed slave asserts an acknowledge (A) by pulling SDA low. 4. The master sends an 8-bit register pointer. 5. The slave acknowledges the register pointer. 6. The master sends a data byte. 7. The slave updates with the new data 8. The slave acknowledges or not-acknowledges the data byte. The next rising edge on SDA loads the data byte into its target register and the data becomes active. 9. The master sends a STOP condition (P) or a repeated START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Figure 4. Writing to a single register. Maxim Integrated Page 9 of 15 Writing Multiple Bytes to Sequential Registers Figure 5 shows the protocol for writing to sequential registers. This protocol is similar to the write-byte protocol above, except the master continues to write after it receives the first byte of data. When the master is done writing it issues a STOP or repeated START. The writing to sequential registers protocol is as follows: 1. The master sends a START command (S). 2. The master sends the 7-bit slave address followed by a write bit (R/W = 0). 3. The addressed slave asserts an acknowledge (A) by pulling SDA low. 4. The master sends an 8-bit register pointer. 5. The slave acknowledges the register pointer. 6. The master sends a data byte. 7. The slave acknowledges the data byte. The next rising edge on SDA load the data byte into its target register and the data becomes active. 8. Steps 6 to 7 are repeated as many times as the master requires. 9. During the last acknowledge related clock pulse, the master can issue an acknowledge or a notacknowledge. 10. The master sends a STOP condition (P) or a repeated START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Maxim Integrated Page 10 of 15 Figure 5. Writing multiple bytes. Maxim Integrated Page 11 of 15 Reading from a Single Register Figure 6 shows the protocol for the I2C master device to read one byte of data from the MAX77278. This protocol is the same as the SMBus specification’s read-byte protocol. The read byte protocol is as follows: 1. The master sends a START command (S). 2. The master sends the 7-bit slave address followed by a write bit (R/W = 0). 3. The addressed slave asserts an acknowledge (A) by pulling SDA low. 4. The master sends an 8-bit register pointer. 5. The slave acknowledges the register pointer. 6. The master sends a repeated START command (Sr). 7. The master sends the 7-bit slave address followed by a read bit (R/W = 1). 8. The addressed slave asserts an acknowledge by pulling SDA low. 9. The addressed slave places 8 bits of data on the bus from the location specified by the register pointer. 10. The master issues a not-acknowledge (nA). 11. The master sends a STOP condition (P) or a repeated START condition (Sr). Issuing a P ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Note that when the MAX77278 receives a STOP, it does not modify its register pointer. Figure 6. Reading from a single register. Maxim Integrated Page 12 of 15 Reading from Sequential Registers Figure 7 shows the protocol for reading from sequential registers. This protocol is similar to the readbyte protocol except the master issues an acknowledge to signal the slave that it wants more data. When the master has all the data it requires, it issues a not-acknowledge (nA) and a STOP (P) to end the transmission. The continuous read from sequential registers protocol is as follows: 1. The master sends a START command (S). 2. The master sends the 7-bit slave address followed by a write bit (R/W = 0). 3. The addressed slave asserts an acknowledge (A) by pulling SDA low. 4. The master sends an 8-bit register pointer. 5. The slave acknowledges the register pointer. 6. The master sends a repeated START command (Sr). 7. The master sends the 7-bit slave address followed by a read bit (R/W = 1). When reading the RTC timekeeping registers, secondary buffers are loaded with the timekeeping register data during this operation. 8. The addressed slave asserts an acknowledge by pulling SDA low. 9. The addressed slave places 8 bits of data on the bus from the location specified by the register pointer. 10. The master issues an acknowledge (A) signaling the slave that it wishes to receive more data. 11. Steps 9 to 10 are repeated as many times as the master requires. Following the last byte of data, the master must issue a not-acknowledge (nA) to signal that it wishes to stop receiving data. 12. The master sends a STOP condition (P) or a repeated START condition (Sr). Issuing a STOP (P) ensures that the bus input filters are set for 1MHz or slower operation. Issuing an Sr leaves the bus input filters in their current state. Note that when the MAX77278 receives a STOP, it does not modify its register pointer. Figure 7. Reading from multiple registers. Maxim Integrated Page 13 of 15 Engaging High-Speed Mode (HS-Mode) for Operation Up to 3.4MHz Figure 8 shows the protocol for engaging HS-mode operation. HS-mode operation allows for a bus operating speed up to 3.4MHz. Engaging the HS-mode protocol is as follows: 1. Begin the protocol while operating at a bus speed of 1MHz or lower. 2. The master sends a START command (S). 3. The master sends the 8-bit master code of 0b0000 1XXX where 0bXXX are don’t care bits. 4. The addressed slave issues a not-acknowledge (nA). 5. The master can now increase its bus speed up to 3.4MHz and issue any read/write operation. The master can continue to issue high-speed read/write operations until a stop (P) is issued. To continue operations in HS-mode, use repeated START (Sr). Figure 8. Engaging high-speed mode. Maxim Integrated Page 14 of 15 Revision History REV NUMBER REV DATE 0 9/17 DESCRIPTION Initial release PAGES CHANGED — ©2017 by Maxim Integrated Products, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. MAXIM INTEGRATED PRODUCTS, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. MAXIM ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering or registered trademarks of Maxim Integrated Products, Inc. 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